Hybrid Pulse-width Modulation Strategy with Reduced CMV Frequency and Improved Switching Loss for Three-Level NPC Converters

High-frequency Common-mode voltage (CMV) excites undesirable bearing current and motor ground leakage current due to capacitive nature of Common-mode (CM) impedance. This high-frequency CMV can be effectively eliminated with Zero-CMV Pulse-width modulation (ZCMV-PWM) schemes at the expense of inferior output harmonic distortion and high switching loss. Hence, a PWM strategy with reduced CMV magnitudes, zero average CMV, and improved output harmonic distortion, namely RCMV1, offers an attractive solution to reduce adverse effects of CMV. However, the CMV frequency of which or the number of variations in CMV values is 6 times per carrier period. Hence, to inherit improved harmonic distortion offered by this scheme while bridging the gap of CMV frequency with respect to ZCMV-PWM schemes, the switching patterns in RCMV1 are modified to reduce CMV frequency. The resulting switching sequences, namely M-RCMV1 suffers high switching loss akin to ZCMV-PWM schemes. As a result, two other types of sequences, namely M-RCMV2 and M-RCMV3 are used along with M-RCMV1 with the information of three-phase currents to minimize switching loss, hence the term hybrid PWM or HRCMV-SLO. In comparison to previously proposed schemes, i.e., ZCMV-PWM with improved switching loss (ZCMV-SLO) and ZCMV-PWM with enhanced output harmonic distortion (ZCMV-THD), HRCMV-SLO produces better output harmonic distortion while achieving comparable and lower switching loss as opposed to ZCMV-SLO and ZCMV-THD respectively. These improvements come with the loss of higher RMS value of leakage current. Simulation and experimental results substantiate the effectiveness of HRCMV-SLO.