A 21-Gb/s PAM-3 Driver Using ZQ Calibration with Middle-Level Calibration to Improve Level Separation Mismatch Ratio

The impedance of the output driver in high-speed memory interfaces should be matched with the channel to secure signal integrity. However, the impedance matching of the three-level pulse-amplitude modulation (PAM-3) driver is not simple, unlike the non-return-to-zero (NRZ) driver because of the non-linearity of the transistor, which deteriorates the ratio of level separation mismatch (RLM). The middle-level ZQ calibration with an additional pull-up PMOS driver can resolve the aforementioned issue. After the calibration, the RLM performance can be improved by correcting the middle level of the PAM-3 signal. This study proposes a single-ended voltage-mode PAM-3 driver with a ZQ calibration for memory interfaces. Our PAM-3 driver with ZQ calibration, including middle-level calibration, was designed through a 65-nm CMOS process. It achieved a data rate and RLM of 21 Gb/s/pin and 0.983, respectively, attaining high PAM-3 signal linearity.