Evaluation of a PUF Embedded in the Delay Testable Boundary Scan Circuit

In recent years, as a security technology against counterfeit IC, Physically unclonable function (PUF) has been proposed that generates unique values based on manufacturing variability information that is difficult to be replicated. However, it requires area overhead to embed the PUF design into an IC to generate unique responses. In order to reduce the area overhead, we propose a method to make delay testing using design-for-testability also function as a PUF. In addition, we applied the unanimous selection method to generate unique values using the proposed method. We fabricated the prototype ICs in two different manufacturing lots and evaluated the stability and uniqueness of the PUF. The results show that different eigenvalues were generated for all chips, including those with different manufacturing lots.