12.8-kSPS Bridge Sensor Read-Out Circuit with Offset Voltage Compensation

This paper presents a 12.8 kilo sample per second (kSPS) bridge sensor read-out circuit. The proposed read-out circuit consists of a three op-amp instrumentation amplifier (IA) and an incremental delta-sigma analog-to-digital converter (ADC). The use of offset compensation capacitor digital-to-analog converters (DACs) and a system-level chopping technique to compensation for offset voltage and reduce
$\mathbf{1}/\boldsymbol{f}$
noise has been proposed for the three op-amp IA. The 18-bit ADC operates at a sampling clock of 4 MHz with a third-order cascade of integrators (CoI) decimation filter. The read-out circuit is implemented in
$0.13 -\boldsymbol{\mu}\mathbf{m}$
CMOS technology and consumes 1.53 mA from a 3 V supply voltage. The offset voltage compensation range is ±720 mV, the input-referred noise is
$2.08 \ \boldsymbol{\mu}\mathbf{V}_{\mathbf{RMS}}$
, and the effective resolution is 14.5 bits at a data-rate of 12.8-kSPS and a gain of 121.