Design and Implementation of Ultra-Low Power I2C-Compatible Bus based on Asynchronous Circuit

I2C bus is a serial communication bus that is widely used in embedded system. It is based on SCL (Serial Clock Line) and SDA (Serial Data Line), to support bi-directional communication between multiple interconnected devices in a master-slave structure. Based on the traditional characteristics and operating principle of I2C protocol, this paper has proposed an innovative I2C-Compatible design for slave based on asynchronous circuit, which is compatible with standard I2C protocol. It is characterized by switchable communication speed, supporting a maximum speed of 3.4 Mbps, ultra-low power and small hardware cost. To ensure reliable communication system, a Schmitt-RC filter and the structure of fine-tuning phase are adopted in our design. After RTL simulation and logic synthesis, the design is verified on FPGA platform communicated with MCU I2C master interface, and finish Placement and Route. The proposed design is fabricated on Dongbu 0.18μm CMOS process, and the test on chip level is carried out after tape-out. The results show that the I2C bus for slave has excellent performance, power and area (PPA) compared with traditional I2C bus, which is very suitable for end-side devices in the IOT and Smart City.

I. Introduction

With the rapid development of IOT, a large number of end-side devices need to communicate with each other. In embedded systems, common communication protocols include I2C, SPI and UART, they have different application scenarios[1]. But how to achieve stable communication, low power and simple circuit structure is always the common goal.