Empirical DC compact model for source-gated transistors using TCAD simulation data

A source-gated transistor (SGT) is a type of thin film transistor (TFT) with unique behaviors. Functionally, the SGT is designed to decrease the saturation voltage at a lower and often more stable saturation current in comparison to a standard TFT, which makes it preferable in some circuit applications. This is achieved by introducing additional effects especially around the source region which differentiate the SGT enough that it cannot be described by a standard TFT compact model. The work presented aims to create the first empirical SGT compact model which may be implemented in DC circuits. This compact model has been developed using the data obtained from an SGT TCAD model.