Performance modeling of a heterogeneous computing system based on the UCIe Interconnect Architecture

In a heterogeneous computing environment, there exist a variety of computational units such as multicore CPUs, GPUs, DSPs, FPGAs, Analog modules, and ASICs. IP Vendors, Engineers, and Scientists working with heterogeneous computing systems face numerous challenges, including integration of IP Cores and components from different vendors, system reliability, hardware-software partitioning, task mapping, the interaction between compute and Memory, and reliable communication.For advanced designs, the industry typically develops a system-on-a-chip (SoC), where different functions are shrunk at each node and pack them onto a monolithic die. But this approach is becoming more complex and expensive at each node. Another way to develop a system-level design is to assemble complex dies in an advanced package. Chiplets are a way of modularizing that approach. Chiplets can be combined with other chiplets on an interposer in a single package. This provides several advantages over a traditional system on chip (SoC) or integrated board, in terms of reusable IP, heterogeneous integration, and verifying die functional behavior.In our work, a system-level model composed of chiplets-IO Chiplet, Low Power Core Chiplet, High-Performance Core Chiplet, audio video Chiplet, and Analog chiplet, are interconnected using Universal Chiplet Interconnect Express (UCIe) standard. We looked at different scenarios and configurations including advanced and standard packages, different traffic profiles, sizing of resources, and Retimer to extend the reach and evaluate events on timeout. We were able to identify the strengths and weaknesses of UCIe interconnect in the scope of mission applications and obtain the optimal configuration for each of the subsystems to meet the performance, power, and functional requirements.