Analysis and Optimization of 16-bit RISC Processor and 32-bit MIPS Processor: A Review

RISC is an instruction set architecture that uses a smaller instruction set as compared to CISC. This reduces the complexity in the implementation of various instructions and in terms reduce the dynamic power consumption, reduce the cycles per instruction and subsequently the cost.32-bit MIPS processor implements 5 stage pipeline that significantly reduces the cycles per instruction and allows the processor to operate at a higher frequency. Complex instruction can be implemented because of the pipeline stages. This paper aims to review various studies done on the comparison and analysis of 16-bit and 32-bit microprocessors. Various models implemented using Verilog HDL and analyzed using Xilinx Vivado, ISE and Modelsim and few designs have used cadence tools for the analysis of the processor models. All these design models are reviewed on basis of the implantation of the processor and parameters that include dynamic power consumption, combinational delay, operating frequency and CPI (cycles per instruction).