Comparative Analysis of Dual-edge Triggered and Sense Amplifier Based Flip-flops in 32 nm CMOS Regime

The article summarizes the outcomes of extensive research carried out on dual-edge triggered flip-flops (DETFFs) and sense amplifier based flip-flops (SAFFs) in relation to their power consumption, delay measurements and area requirements. The research focused on four of the most advanced flip-flops (FFs) currently available, and simulations were conducted in SPICE using 32 nm CMOS technology. The results showed that Lee's FF had better power efficiency at data activities of greater than 25% whereas Lapshev's FF could be used for circuits with less data activity. Jeong's FF had better speed efficiency at higher voltages. Lee's FF also had the best power delay product (PDP) followed closely by Jeong's FF at nominal conditions. Additionally, Jeong's FF outperformed other designs in terms of area overhead.