Comparative Analysis of EEPL and CPL Techniques Using 2:1 Multiplexer Based on 18nm FinFET Technology

The primary concerns in VLSI circuit design technology are usually power usage and propagation delay optimization. In this paper, we have proposed energy-economized pass-transistor (EEPL) techniques and complementary pass-transistor logic (CPL) based on 2:1 multiplexer (MUX) using FinFET 18 nm technology. The result shows the value of Power Delay Product (PDP) for EEPL based on multiplexer at 1.2 V is
$1142.04\times 10^{-4}$
(J), at 1 V is 425.94 X 10
⁻¹⁴
(J), and at 0.8 V is
$66.3\times 10^{-14}$
(J). While, Energy Delay Product (EDP) for EEPL-based MUX at 1.2 V is
$289.19\times 10^{-20}$
(Js), at 1 V is
$107.86\times 10^{-20}$
(Js) and at 0.8 V is
$16.79\times 10^{-20}$
(Js). The PDP for CPL-based MUX at 1.2 V is
$2336.37\times 10^{-14}$
(J), at 1 V is
$1234.98\times 10^{-14}$
(J), and at 0.8 V iS
$538.01\times 10^{-14}$
(J). The EDP for CPL-based MUX at 1.2 V is
$3107.39\times 10^{-20}$
(Js), at 1 V is
$622.77\times 10^{-20}$
(Js), and at 0.8 V is
$271.28\times 10^{-20}$
(Js). The EEPL-based MUX outperforms the CPL technique. Both of these MUXs can be used in health care and adiabatic biomedical applications.