Design and Implementation of BIST Architecture for low power VLSI Applications using Verilog

The proposed BIST architecture focuses on minimizing power consumption during the testing phase while maintaining high fault coverage. It leverages the capabilities of the Verilog hardware description language to model and simulate the design. The research investigates various power reduction techniques, including test pattern compression, selective clock gating, and power-aware test scheduling, to optimize power consumption during testing. This research paper presents the design and implementation of a Built-In Self-Test (BIST) architecture specifically tailored for low-power Very Large-Scale Integration (VLSI) applications. The increasing demand for energy-efficient electronic devices and the proliferation of portable systems have necessitated the development of power-aware design techniques. BIST, a onchip testing technique, plays a crucial role in ensuring the quality and reliability of integrated circuits. The implementation is performed on a field-programmable gate array (FPGA) platform, demonstrating the feasibility and practicality of the proposed design. The research contributes to the field of low-power VLSI design by providing a comprehensive BIST architecture that effectively reduces power consumption during testing. The proposed design is compatible with standard Verilog synthesis and is readily applicable to a wide range of low-power VLSI applications. The findings from this study can guide designers in developing energy-efficient and reliable integrated circuits, promoting sustainability, and extending battery life in portable devices.