Introduction
As increased power consumption causes a linear rise in chip temperature, there is a rising need for low-power approximation multipliers. Power dissipation and excessive power consumption must be decreased in order to lengthen the battery life of devices, making this the main goal of current VLSI circuit designs. The operands are divided into two m-bit segments according to the static segmentation idea. This method makes hardware implementation more simpler and significantly decreases power consumption.Even though it causes variances in the operands' ultimate products, precision is not a greater problem than increased power consumption. Based on the idea of static segmentation, the approximate recursive multipliers suggested in this paper are about the logic of designing approximate multipliers in which the inner multiplier is also segmented. Compared to non-recursive multipliers, recursive multipliers can reduce power usage. Field programmable gate arrays are used in this work. The Artix 7 board is utilised in this case because it offers exceptional performance when compared to other FPGA families [1]. Additionally, this paper compares the power use of recursive and non-recursive multipliers (both based on SSM), the outcomes of their simulations, their LUTs, and their utilisation.