Efficient Transistor-Level QDI Asynchronous Switch for Neuromorphic Systems

Neuromorphic systems benefit from quasi-delay-insensitive (QDI) asynchronous interconnection networks, which offer low power consumption, improved robustness, and scalability. However, when designing Networks-on-Chip (NoC) routers with standard multiplexer cell-based switches, asynchronous circuits suffer from area overhead and power consumption. To address this issue, we propose a transistor-level asynchronous switch design that reduces the number of control signals, resulting decrease in transistor count by 36%. By decomposing those control signals, we achieved a power consumption reduction of 77% and improved delay by 18%. The transistor-level switch was designed using the Sense Amplifier Half-Buffer (SAHB) logic family, and its performance was simulated using models for 65-nanometer CMOS technology.