A High-Speed Charge-Injection based Double Tail Latch for Decision Feedback Equalizer (DFE)

This paper presents the design and analysis of a modified double tail latch (DTL) with reduced delay for DFE of serial links. The proposed DTL structure incorporates channel charge-injection technique to minimize the clock-to-Q delay of the latch. The proposed latch implemented in UMC 65 nm CMOS technology has a lesser clock-to-Q delay compared to the conventional DTL structure. The clock-to-Q delay of the proposed latch is approximately 15% lesser compared to that of the conventional DTL structure. The proposed latch consumes 313 $\mu$W at a sampling frequency of 5 GHz and a supply voltage of 1 V. It has a clock-to-Q delay of 36 ps when operated with $V_{CM}$=600mV and $\triangle V_{IN}$=100mV.