CMOS Continuous-Time Integrator with Capacitance Multiplier

This paper presents a CMOS continuous-time integrator using a capacitance multiplier for a smaller chip area. It is based on a modified local-feedback amplifier and mitigates a power dissipation issue in the impedance multiplication capability. Compared to integrators based on an operational amplifier or a transconductor, the proposed circuit has both good linearity and area efficiency under the condition of the lower supply voltage. The simulation results show 50% reduction of the capacitance and 33% of power dissipation for the same time constant.