Error Resilient Sleep Convention Logic Asynchronous Circuit Design

This paper proposes a resilient QDI Sleep Convention Logic (SCL) asynchronous architecture, capable of recovering from single-event radiation-induced effects such as single-event upset (SEU) and single-event latch-up (SEL). The recovery procedure is detailed in the paper, and it has been categorically proven that the safety and liveness of the SCL circuit will not be affected during a SEL or SEU. A resilient SCL 4×4 array multiplier was implemented based on the proposed architecture using a 32-nm CMOS PTM model. Compared to a similar resilient NULL Convention Logic (NCL) architecture, the proposed design requires ~20% fewer transistors, consumes 2.4 times less energy per operation, and dissipates ~3 fold less power during idle stages.