Advanced Packaging Design Platform for Chiplets and Heterogeneous Integration

Chiplets integration offers a compelling value proposition for yield improvement, IP reuse, performance and cost optimization. Various advanced packaging technologies such as 2.5D Si TSV interposer, Fanout RDL organic interposer and 3D hybrid bonding have been deployed for chiplets and system heterogeneous integrations. Meanwhile, integrating multiple chiplets with diverse functions into a single package has also created a demand for advanced packages with higher density interconnects and larger footprint body sizes. How to optimize the layout to get the optimal performance among the chiplets has become very critical. In addition, high density and complex connectivity in advanced packaging cause more challenges by using traditional EDA tools for packaging design and assembly manufacturing validation. Furthermore, the die-to-die interconnects for chiplets integration are usually proprietary links from different customers, thus also create more design boundaries and limit the adoption of advanced packaging technology. In this paper, a new chip-to-package hybrid design platform for chiplets integration using advanced packaging technology was introduced. The design platform was utilized to complete the routings of ultra-high density I/O in 2.5D Si interposer and Fan-Out RDL organic interposer. Compared with the traditional package level design platform, the new hybrid design platform had reduced the design cycle time and improved design accuracy. Additionally, this platform had leveraged and validated the open standard Die-to-Die interconnects through the UCIe (Universal Chiplet Interconnect Express) ecosystem. Good electrical performance was achieved and met the requirements under the pin speed of 32Gbps for both fanout RDL organic interposer and 2.5D Si TSV advanced packaging technologies. Furthermore, a new packaging process design kit (PDK) had been developed to provide IC and system designers with advanced packaging design rules. Finally, this paper elaborated the design challenges and collaboration with system and IC design companies on chiplets integration from the perspective of OSATs.