Demonstration of a Power-efficient and Cost-effective Power Delivery Architecture for Heterogeneously Integrated Wafer-scale Systems

In recent years, wafer-scale engines have emerged as a promising solution for achieving high performance computing (HPC), thanks to their advantages on form factor and scalability. By building a wafer-scale system with fine-pitch die-to-wafer bonding, it is possible to achieve high computing power, large memory capacity, and fast and efficient access to this memory, while ensuring high manufacturing yield and low design complexity. Large wafer-scale systems, however, make enormous demands on power (≥ 50 kW for a 300 mm diameter wafer), and methods to deliver this power efficiently, uniformly, and cost-effectively have not been fully realized yet. Compared to silicon, Gallium Nitride (GaN) switches promise higher conversion efficiency and higher power density, due to GaN's large bandgap, large breakdown electric field, and high electron mobility. In this paper, a dielet-on-GaN interconnect fabric (GaN-IF) vertical structure was demonstrated with a ≤ 10 µm metal bonding pitch for the future three-dimensional integrated voltage regulator (3D-IVR). This allows for intimate integration of the GaN switches with high-performance CMOS logic and passives in the substrate. An average shear force of 160.76 N was achieved on a dielet-to-wafer assembly with a dielet size of 4 mm
²
. An effective specific contact resistance of 0.13 Ω-µm
²
was measured for the Cu-Cu bonding interface. A reliability test was performed, showing a resistance change of < 4%. Photoluminance, x-ray diffraction, and Raman spectra were measured to prove that our fabrication and bonding processes are not degrading the quality of the GaN layer. Additionally, a novel architecture is demonstrated, which allows an efficient delivery of power to the wafer-scale system through a dielet-side power delivery network (PDN) that does not require through-silicon vias (TSVs) - which are costly and necessitate the thinning of the substrate. A robust integration process flow for dielet-side power delivery was developed and optimized to obtain desired mechanical and electrical properties of the assembled structure. Power platforms were flip-bonded to the front side of the die-to-wafer assembly to form daisy chains. This is the first work that demonstrates a power-efficient, cost-effective, and heterogeneous power delivery architecture for wafer-scale systems.