Simulation-Assisted Board Level Solder Joint Reliability Optimization for Large 80mm+ 2.5D Devices

The growing reliability risk of board-level solder joints for large body size semiconductor devices requires the evaluation of new countermeasures at multiple stages of the component and system development process. For high power devices, the challenge is further elevated due to the interaction with thermal solution hardware. In this study, a Reliability Improvement Measure (RIM) is deployed at the assembly level, and its performance is compared with a design that does not incorporate this measure. Assemblies with and without RIM are evaluated using temperature cycling, and the characteristic life and solder microstructure are analyzed at the conclusion of the test. Numerical simulations are adopted to provide insight into performance differences. For both configurations, corner solder joints experience the highest level of stress and accumulation of damage. However, the adoption of RIM reduces the level of stress significantly, thereby decreasing fatigue and extending the life of the solder joints. At the microstructure level, recrystallized grains are observed at the component side of the solder joints for both configurations. However, the extent of recrystallization and cracking are more pronounced in the units without RIM. The results from this work highlight the importance of conducting early reliability assessment and demonstrate that product level reliability can be effectively managed with the appropriate solutions.