A Novel Stacked-via Cu/ELK Interconnection Design Configuration to Enhance Advanced Si Packages Reliability Performance

In recent years, stacked-via Cu interconnect with extra low-k (ELK) dielectric material had been applied to reduce power consumption and further enhance device performance, especially for advanced flip chip packages with Cu bumps. Under thermal cyclic loading, the bump will encounter cyclic shear force and transfer stresses from substrate to die due to coefficients of thermal expansion (CTE) mismatch between die (~2.8 ppm/°C) and substrate (~17 ppm/°C), which induces the horizontal expansion differences between die and substrate and results in component warpage. If the bump with higher modulus such as Cu bump, the major Cu pillar in Cu bump has smaller deformation which will increase the stresses transfer from substrate to die and induce higher die internal stress. Due to the rigidity of stacked-via Cu/ELK structure, it may cause large via deformation and affect stacked-via integrity through bump under cyclic package warpage. This work investigated high-performance flip chip ball grid array (HFCBGA) package with stacked-via Cu/ELK interconnection reliability performance under JEDEC TCB reliability test condition. A thermo-mechanical stacked-via Cu/ELK stress analysis is conducted to evaluate the thermally induced stresses in the Si/package. A three-dimensional (3-D) nonlinear finite element method is applied, and a three-level of specified boundary condition (SBC) of global-local technique is developed. Meanwhile, Project Moiré warpage measurement is conducted to calibrate modeling predictions. From stacked-via stress analysis in this study, if top via can be offset from top-1 via, via deformation is absorbed and stacked-via integrity can be well protected. Higher bump density, higher ELK metal density, and larger polyimide opening size could also relieve stacked-via thermal stresses significantly.