Heterogeneous Radio Chiplet Module for 5G Millimeter Wave Application

While heterogeneously integrated packages for high performance computing have been presented, radio frequency (RF) applications have received less attention. In this work, we present an evaluation of a package for integrating two RF analog chiplets and a digital chiplet in a single high density fan-out package for 5G millimeter wave (mm-wave) applications. The two RF chiplets control antenna elements and the digital chiplet carries out the necessary signal processing. The chiplets were attached to a High-Density Fan-Out (HDFO) package with 2um/2um line width/space wiring designed for chiplet to chiplet communications. The HDFO was attached to a laminate, molded and a heat spreader (lid) was attached to realize a robust package. The RF chiplet was designed in 22FDX® technology and was
$\mathbf{3} \times \mathbf{16.5}\mathbf{mm}$
in size. The digital chiplet was designed in 12LP technology and was
$\mathbf{4.5} \times \mathbf{16.5}\mathbf{mm}$
in size. The chiplets were thinned to 0.3mm and attached to High-Density Fan-Out with 25um diameter, 40um tall micro-pillar bumps. The chiplets were arranged with one RF chiplet on the North side, the digital chiplet in the center and the second RF chiplet, which was 180 degree rotated RF chiplet, on the South side. The gap between the chiplets was 70um. The chiplet to chiplet wiring was done with 2um wide traces that connected to 55um pitch micro-pillar bumps. The bump pitch was 55um at the edges of chiplets to facilitate a high density of wiring between the chiplets; elsewhere the bump pitch was 150um. The HDFO had four routing layers, front side pads for receiving micro-pillar and back side under bump metal for solder balls. The HDFO was reflow attached to a laminate. The laminate had four metal layers for routing. Capacitors for power supply filtering were also attached to the laminate. This was molded and a 0.5mm thick, copper lid was attached to the top of the package to remove heat from the chiplets. The thin RDL layers in the HDFO substrates presents design challenges for RF and mm-wave signal transfer and understanding these design challenges and the impact of them becomes important. The package therefore included several test structures to evaluate the performance impacts of different parts of the design stack, both in the package and the FC-CSP package. The package was subjected to JEDEC stress tests to assess the reliability. Electrical readouts of daisy chains were acquired to monitor interconnect failure or degradation. Daisy chains were included in the FC-CSP laminate, HDFO, and at die level to test interconnects and reliability. Groups of daisy chains were used to differentiate between early failures and extended stress failures. The packages passed moisture level 3 pre-conditioning (40 parts) and unbiased highly accelerated tests (20 parts). The packages were assembled to PCB for Accelerated Temperature Cycling test (JESD22-A104 condition G)