Design and Analysis of 3D Heterogeneous Chiplet Stack for RF Front-End Module Minituarization

This paper presents the design, simulation, analysis and characterization of a heterogenous 3D integration approach for miniaturization of RF front-end modules. The 3D integrated stack consists of two dies using different technologies. The first die is a low-noise amplifier (LNA), designed and fabricated in 130nm 8SW RF SOI Global Foundries technology. The second die is a duplexer built using Qorvo's BAW technology. The first die is used as a base on which the second die is mounted. To achieve this integration a redistribution layer (RDL) has been designed and built on the backside of the first die. Through silicon vias (TSV) have also been designed and built to allow the top die to be routed and interconnected to the bottom die as well as to the outside world. The final size of the integrated module is 1×1.4×0.45mm
³
. This paper discusses in detail the design process of the module, the simulation models with the associated simulation results. It also presents measurement results obtained from a test vehicle design to extract the parasitics and equivalent circuit of the TSV through the SOI wafer. The signal losses measured through the test structures, that emulates the 3D stack environments, are below 0.2dB at 2GHz. These results are promising and give us confidence for the final functional module testing.