Extremely Large Area Integrated Circuit (ELAIC): An Advanced Packaging Solution for Chiplets

The slow-down of Moore's-Law-related lithographic scaling in high-density semiconductor integrated circuits has created a major impact on the design of computing hardware architecture. Computer architects are exploring heterogeneous assemblies of specialized chips (called “chiplets”) as an alternative way (i.e., “More-Than-Moore”) to provide the increasing computing capability needed to satisfy our data intensive future. Microelectronics packaging is evolving to meet the computing demands of increasing power and performance in ever smaller packages. To accomplish this, new packaging structures need to be able to integrate more chiplets with smaller technology nodes (5-, 7-, or 10-nanometer), higher I/O counts, and smaller interconnect pitches, while reducing the overall assembly footprint. This paper describes a new extremely large area integrated circuit (ELAIC) solution suitable for combining multiple chiplets of varying type (e.g., memory, ASICs, CPU, GPU, power conditioning) into a single package on a common interconnect platform. The ELAIC approach helps to rearchitect heterogeneous chip tiling for developing highly complex systems having desired circuit density and performance. Recent work on large-area superconducting integrated circuits to join multiple individual die is highlighted, with particular attention paid to the processing of the high-density electrical interconnects formed between the individual die. A variety of ELAIC assemblies were fabricated and characterized using several techniques (i.e., scanning-electron microscopy (SEM), optical microscopy, confocal microscopy, X-ray) to investigate the integration quality, minimum feature size, silicon content, die-to-die spacing, and gap filling. Silicon dioxide, benzocyclobutene (BCB), epoxy, polyimide, and silicone-based dielectrics were used for gap fill, via formation and redistribution layers (RDLs). For the ELAIC approach, the thermal stability is improved by reducing the die-to-die (D2D) gap and increasing the silicon content, allowing assemblers to mitigate the problem of mismatch in coefficient of thermal expansion (CTE) for different substrates/modules integration schemes, which is important for allowing the broad temperature range stability from reflow to operation at room or even cryogenic temperatures. ELAIC technology facilitates more space-efficient designs and can accommodate most heterogeneous die without compromising stability or introducing CTE mismatch or warpage. A variety of heterogeneous chips were used to fabricate ELAIC modules. The present process allows fabrication of ELAIC buildup layers having thickness in the range of 1–10 microns, which allows packaging structures having both finer pitch and higher density. The processes and materials used to achieve smaller feature dimensions, satisfy stringent registration requirements, and achieve robust electrical interconnections are discussed.