Area Efficient Implementation of Software-Defined Radio using FPGA

Due to the fact that the Software-defined radio (SDR) will be used in the field, it is essential that it has a low energy consumption and effective noise suppression. The proposed system is software define radio-Transceiver of OFDM implementation in FPGA which is used to reduce memory size and reduce power consumption. In order to get started monitoring the amount of energy used, several approaches were examined for each component. The amount of bits that were used to characterize the signal was decreased so that the influence it had on power consumption could be better understood. As a result of this modification, the amount of power used decreased from 3.01mW to 2.15mW. After making some little modifications to the algorithm selection, the power consumption was brought down to 2.15 mW. After that, the clock rate was slowed down for many parts of the system, which resulted in a reduction in the amount of power used.