Low Power and High Speed Charge Pump based Dual Stage Dynamic Comparator using 45nm CMOS Technology

A comparator is a key component in variety of applications such as data converters, mixed signal systems, signal processing, digital I/O circuits, biomedical devices, memory sensing circuits, and so on. These applications frequently necessitate low-power, high-speed and low-offset comparators. In particular for signal processing applications, enhancing the performance of data converters depends on the accuracy of comparators. The most effective way to enhance the sampling rate of data converters is to improve comparator speed. A pre-amplifier with a charge pump is used in the proposed dynamic comparator, followed by a decision circuit and an output stage. The simulated results demonstrate that comparator has achieved a low power consumption of 13.13μW with a delay of 85.54ps making it more suitable for data converters. The comparator operates with clock frequency of 1GHz and a supply voltage of 1V, and it is simulated in 45nm CMOS technology using the Cadence virtuoso tool.