A Spur Reduction Architecture for Integer-N Subsampling PLLs

In this work, a reference spur reduction method for integer-N subsampling PLLs is presented. A dual-loop architecture is implemented with the loops operating at opposite phases of the oscillator. A feedback network with error amplifier is there to equate the control voltages of both loops. Finally, the control voltages are added and applied to the oscillator, which is quite clean compared to that of the individual loops, aiding in spur reduction. The design is implemented in CMOS 90 nm technology with a oscillator frequency of 1 GHz. Reference spurs are at offsets of 100 MHz and post-layout simulation results show that the highest spurs are at -45dBc.