Floorplanning and Comparative Analysis of 16-bit Synchronous Up/Down Counter in Different CMOS Technology

In the digital domain, counters are an essential sequential circuit elements. In this paper, a 16-bit synchronous up/down counter is examined at different CMOS technologies for power, delay, and area occupied by the cell. The main aim is to study the effects of different CMOS technologies on leakage power, dynamic power, delay, and chip area. After simulation, results showed that at 45nm CMOS technology, total power consumption is 75.71% less as compared to 180nm CMOS technology. In terms of cell area and delay again 45nm CMOS technology showed better results. Further, the technology scaling substantially decrease power consumption and increase the number of transistors that can be integrated into a chip.