An Extremely Low-voltage Floating Gate Artificial Neuron

This paper presents an artificial neuron design, based on a floating gate (flash) transistor array, that operates with an extremely low supply voltage domain
$VDD_{lo}$
(which we chose to be 100 mV). Neuron inputs and outputs are in another domain
$VDD_{hi}$
(which we chose to be 0.8 V). Since
$VDD_{hi}$
is the nominal supply voltage for our process, input and output data can be stored in registers without the need for level shifters. Neuron weights are stored in-memory in a flash transistor array, using a novel differential conductance encoding scheme. Our neuron performs operations in the analog voltage domain. We compare our design against a recent flash-based mixed-signal neuron design, which has reported the best results (in terms of power and energy, with insignificant error) thus far. We demonstrate that our neuron design beats the previous design in static power consumption
$\mathbf{(52.9}\times$
less), static energy consumption
$\mathbf{(1.41}\times$
less), and layout area (44% less). The goal of this work is to design a low-power, low-energy neuron which could be used to implement an entire Neural Network (NN). Our focus is on the neuron, and not the whole NN.