Selective Binarization based Architecture Design Methodology for Resource-constrained Computation of Deep Neural Networks

In this paper, we introduced a novel selective binarization based architecture design methodology for the compute-intensive deep neural networks (DNNs) implementation on memory-constrained platforms with insignificant compromise in accuracy. To demonstrate the advantages of our proposed architecture design methodology, we performed a detailed layer-wise performance analysis of a DNN with the help of metrics like memory savings and accuracies. Subsequently, we validated the proposed design methodology by implementing it on the resource-constrained AMD-Xilinx Kintex-7 field-programmable gate array (FPGA) chip for the considered DNN. A thorough analysis of our architecture design methodology results shows a significant memory savings of about 93% or compression of 15.7× with less than a 1% marginal reduction in accuracy.