Stability Analysis of 6T SRAM at Deep Cryogenic Temperature for Quantum Computing Applications

CMOS circuits operating at cryogenic temperature are gaining interest as one of the most promising approaches to efficiently scale up quantum processors in near- and medium future. However, there are major challenges such as (1) strict power dissipation limit at 4K plate due to the limited cooling power of the dilution fridge and (2) significant shifts in CMOS device behavior (i.e. variations, threshold voltage, charge carrier mobility and sub-threshold slope) which are not accurately captured in the standard BSIM models from the foundries. Although there have been extensive works experimentally characterizing and analyzing CMOS transistors at ∼4 K, there is a lack of digital and memory subsystem study. Since on-chip SRAM is one of the most power-consuming and the most vulnerable element in cryogenic SoC, this work analyzes the stability of low-voltage 6T-SRAM at deep cryogenic temperature (i.e 77K and 8K), in comparison with 300K operation. Our DC analysis showed that in general, Write static noise margins of the SRAM cell improves when temperature changes from 300K to 8K, even at low-voltage condition. Regarding the Read static noise margin, our simulation showed that the inverters exhibit pseudo-static hysteresis and interestingly this leads to an improvement of read static noise margin of the cell, similar to what observed in a Schmitt-Trigger SRAM. These results suggest that although CMOS transistors exhibit higher threshold voltage in cryogenic temperature, it is still possible to operate the SRAM at low-voltage for power saving in quantum computing applications.