On the Implementation of Data Security for Neurostimulation Devices

Neurostimulation devices have emerged as a promising therapeutic solution for a wide range of neural disorders ranging from depression, epilepsy and Parkinson's. This paper delves into the data security aspect of such devices. The work provides a comparative study of the two popular ciphers namely, DES-64 and AES-128 in the context of neurostimulators. The two cipher algorithms are implemented on an FPGA and verified functionally for the stimulation functionality. The DES-64 and AES-128 decryption engines along with the data interface and stimulator digital core were implemented on a 65nm CMOS technology using two MOS flavors namely low-VT and regular-VT low-leakage devices. Post-layout simulation results show that the low-VT design outperforms the regular-VT design for data rates above 1Mbps. Finally, simulation results show that the AES-128 consumes 28% extra power compared to DES-64, however with a superior data security margin.