An ADPLL with Two-Point Modulation Gain Calibration for 2.4GHz ISM-Band in 40nm CMOS

In this work, an all-digital phase-locked loop (ADPLL) based on a loop counter with two-point modulation (TPM) gain calibration for 2.4GHz ISM-band is implemented. The proposed symbolic least mean square error calibration algorithm can effectively realize the low cost and high efficiency of TPM calibration. Meanwhile, an effective low delay time digital converter (TDC) decoder and a GFSK modulation signal generation circuit with adjustable bit rate is realized on the chip. The ADPLL prototype is designed in 40nm CMOS which occupies a core area of 0.325 mm
²
, The simulation result shows that the phase noise is −117.7 dBc/Hz at 1MHz offset from 2.4GHz, and the power consumption is 5.6mW at 1.1V supply voltage.