A 11-ns, 3.85-fJ, Deep Sub-threshold, Energy Efficient Level Shifter in 65-nm CMOS

This paper presents an energy-efficient level shifter, which up-convert to 1.2 V from 0.3 V. The proposed architecture is based on single-stage differential cascode voltage switch logic (DCVSL) with multi-threshold transistors. A self-adapting pull-up (PU) network is used, which increases the switching speed and reduces energy consumption. To further improve the energy efficiency, a split-input inverting buffer with a higher threshold voltage is used in the output stage. The proposed design is implemented in 65 nm CMOS technology for
$V_{DDL}=300\text{mV}$
and
$V_{DDH}=1.2$
V. To up-convert from 0.3 V to 1.2 V, the proposed architecture has an average propagation delay of 11 ns and achieves 3.85 fJ of energy per transition at 1 MHz operating frequency.