I. Introduction
The advancement in the CMOS technology has lead to the high-level integration with high power density in the system-on-chips (SoCs) and battery-powered devices. These devices are prone to multiple hotspots on the chip and should be monitored for optimal performance and system reliability. Modern processors employ multiple temperature sensors for continuous on-chip thermal monitoring to avoid hotspots [1]. State-of-the-art temperature sensors are broadly divided into two main approaches based on sensing element (SE), a) current (SE)-to-frequency-to-digital code, and b) frequency (SE)-to-digital code, as shown in Fig. 1. In the prior one, high linearity has to be maintained in both stages, i) while generating a temperature-dependent current and ii) on converting it to frequency, which requires a complex architecture with more power consumption and area. Besides, we need to employ complex calibration techniques to reduce the process variation in both sensing, and frequency blocks [1]–[3]. In the latter approach, the frequency generator acts as a sensing element relaxing the need for linearity with low power and less complex architecture [4], [5]. The design in [4] used two ROs with MOSFETS of different to generate a proportional to absolute temperature (PTAT) frequency ratio . However, it requires an off-chip non-linearity removal technique to mitigate the mismatch effects caused due to variation in . Also, it is less technology scalable due to usage of various MOSFETS. The design in [5] presented a single leakage-based oscillator with PTAT frequency. It used an temperature-independent external reference clock for converting it into a TCODE, which means this design needs a reference clock available beforehand.
State-of-the-art temperature sensing techniques, a) temperature - current - frequency - digital code (3-step process), b) temperature - frequency - digital code (2-step process)