Design of an IP core for motion blur detection in fundus images using an FPGA-based accelerator

This paper focuses on applying an algorithm for real-time blur detection in fundus images via hardware acceleration. Blur in fundus images is caused due to many factors, but most of the time, with a reasonable degree of accuracy, they could be classified as motion blur. A motion blur could be modelled as an image convolved with a blur transfer function. Blur metrics are identified via techniques such as Haar DWT as it gives reasonable accuracy for most types of linear blur. First, a hardware architecture using Verilog HDL is created that computes the edge maps of images. This architecture is based on a novel algorithm that encompasses a series of Haar DWT Units. The simplicity and flexibility in this proposed architecture allow any kind of software or hardware platform to integrate the proposed model with very little to no modification, onto them. Subsequently, the IP core for the proposed architecture is developed, which can be further extended into an SoC, which can then be programmed onto a suitable FPGA system, which could then be uploaded with images that get classified as blurred and clear images. The on-chip processing system of the FPGA-SoC reads the image data and sends it to the Blur Detector IP via the DMA IP in the SoC. The whole process uses a double-buffered design in order to reduce IP stall time and increase efficiency.