Design Of Low Power & High-Speed Multiway Merge Sorting Networks For Median Filter

Sifting is an important activity in a wide range of applications, including image, video, and sensor fusion, ATM and network shifting, statistical modeling, forecasting, intelligent systems and robotics, and data gathering and databases. The proposed work’s main objective is to develop a new data comparison technique that offers a limited technique for ordering or ranking networks based on speed, energy, and region. In this research, we offer a new area-efficient and comparative estimator for median filter application. This proposed system was written in Verilog HDL, simulated with Modelsim 6.4 c, then synthesized with the Xilinx tool. The suggested system is built on an FPGA Spartan 3 XC3S 200 TQ-144. The design of a low-power, high-speed multiway merge sorting network for median filter applications is presented in this study. To achieve a balance between power efficiency and sorting performance, the suggested network employs a hybrid sorting strategy that incorporates the benefits of both parallel and serial sorting algorithms. The network is built utilizing a hybrid of digital and analogue circuit approaches, resulting in substantial power savings while retaining good sorting performance. The suggested median filter is assessed using simulation and experimental data, which show that it is more successful than existing techniques at lowering power consumption and improving sorting speed.