Design of Physically Unclonable Function for FPGA Identification

Security is paramount when it comes to communicating between devices, particularly the Internet of Things edge devices. Low level security is a great solution to low power devices, as there is no need to run complex algorithms for key generation. Physically Unclonable Functions (PUFs) are such designs that can't be cloned and are resistant to physical intrusion attacks. Unclonability comes from the physical parameter mismatch that is not controllable by the foundry, delay is one such parameter. Ring Oscillator (RO) based PUF is a type ofPUF where the delay parameter is exploited. A circuit for IntegratedCircuit (IC) identification is proposed using the RO PUF. This design can't be cloned and hence acts like a fingerprint for the IC. A design with 4 instances of basic RO chain is proposed thereby increasing the bits generated to identify a [Field Programmable Gate Array (FPGA). This increases the security of the design and reduces the risk of being broken by a machine learning attach. Various design challenges and their solutions are discussed to make the design possible using tools that does a lot of optimization. The proposed design is tested using Basys 3, Xilinx 7 Series FPGAs.