A CMOS Threshold Voltage Monitoring Sensor

A real-time CMOS threshold voltage (V
TH
) monitoring sensor is presented. A threshold-voltage extractor architecture with a nested feedback loop technique is exploited, to provide input-free operation. The topology presents high immunity to supply voltage variations and self-compensation for second-order effects. The V
TH
monitoring sensor is designed and fabricated in a 0.18-μm CMOS standard process, occupying 0.0013 mm
²
of silicon area. Experimental results validate the performance of the proposed circuit. A maximum V
TH
deviation error of 0.25% is observed, for 2.2 V – 3.6 V supply voltage range, depicting the proposed rea-time V
TH
monitoring sensor as an area and accuracy optimum topology.