Research on Chip Resource Layout Based on PISA Architecture

The programmable switching chip overcomes the defect of the fixed function of the traditional chip, and has the characteristics of high programmable rate. It has broad prospects in the future network. In the PISA architecture of the current mainstream programmable switching chip, the compiler needs to divide the P4 program into basic blocks and arrange them at all levels of the pipeline. However, due to many complex constraints within and between pipelines, chip resource layout has become a thorny issue in the chip industry. Based on the actual data, this paper builds a specific model to solve the resource allocation problem of PISA architecture chips.Aiming at the resource layout problem of PISA architecture chip, a series of control dependencies, data dependencies and resource constraints are given. In this paper, a single objective integer programming model is established and an algorithm is given to solve it. An optimization framework is proposed to meet resource constraints and control dependence and data dependence. The framework is basically built through the control dependency solving algorithm based on graph search, the data dependency solving algorithm based on preprocessing, and the basic block pipeline hierarchical allocation algorithm under resource constraints. The first two algorithms are used to search the control dependency and data dependency between basic blocks. The latter can finally get the optimized pipeline number under the condition of satisfying the control dependency and data dependency and resource constraints. Through this algorithm framework, a 51 level pipeline basic block layout scheme is obtained.On the basis of the above research, this paper adds the condition that different execution processes in the same pipeline can share resources.