A Unique Approach towards Serial Parallel Multiplier to Reduce Number of Components

In this paper a creative and modified design of serial parallel Multipliers (SPM) has been proposed. The circuit architecture of the existing serial parallel multiplier has been modified to reduce the resource constraints and also to improvise on area, power and delay. The proposed SPM architecture reduces the complexity of existing architecture i.e by reducing number of blocks of implementation. The existing SPM and proposed SPM both are realised using verilog code and tested in Quartus 18.1 environment. It shows improvement in consumption of resources, area and power. Further the proposed architecture can be extended for optimisation of latency and delay constraints. The test was carried out for both 4 bit and 8 bit SPM architecture design. In comparison with existing architectures the proposed method shows 18.5% reduction in consumption of resources. The proposed architecture can find utmost applications in various domains where digital multiplication is critical.