Design of Quaternary Inverter Using 32nm SOI Technology

In VLSI design due to continuous increase in chip density and decline in size of CMOS technology node, number of interconnects become one of the major concern. To avoid complexity of interconnects, Circuits are designed using Multi Valued Logic (MVL). MVL is efficient over binary to address the problem of interconnect density caused by huge number of transistors per chip. Different structures like Finfet, Silicon on Insulator (SOI) are preferred over bulk CMOS due to short channel effect. In this paper Quaternary inverter are designed using CMOS, SOI and CNTFETs using 32nm technology. Designs are verified by Synopsys HSPICE to compare power, delay and power delay product. Inverter designed using CNTFETs is more efficient compared to other circuits whereas SOI shows more delay compared to CMOS and CNTFETs..