Designing Torus and HyperCube Network-on-Chip Systems Based on MPLS Networking Technique

This paper describes a simulator for two types of network-on-chip designs that employs the MPLS as an essential communication tool for switching and routing at the packet level inside the chip of multiprocessing system on chip implemented as a network-on-chip. Modeling and simulation results demonstrated the when using MPLS with network-on-chip system efficient results obtained with reduced latency, less packet error ratio, and fault tolerance achieved with the nature principle of the MPLS.