Five Stage Pipelined MIPS Processor Verification Interface and Test Module using UVM

The Million Instructions Per Second (MIPS) processor design is one of the very earlier foundation of designs for modern-day processor. This brings various different basic concepts of modern-day computing such as Pipelining, Data Dependency handling, and forwarding to one place to enhance the capabilities and speed of processing. This research work proposes to verify few functionalities of a five-stage pipelined MIPS processor. The design under test comes with a total of 16 instructions with a total of 49 variants, 5 pipeline stages, and a hazard unit. Also, this research study presents the verification of this design. The functionality of each instruction is tested using Constrained Random Verification and for implementing verification techniques in System Verilog Unified Verification Methodology (UVM) is used.