Five-Stage Pipelined MIPS Processor Verification Driver Module using UVM

This research study presents the five-staged pipelining concept with automation in functionality verification of the MIPS processor driver module, which makes the process interlinked to organize the activity in a parallel manner. As the design complexity in RTL increases with the current advancement of VLSI technology, it creates an impact on the verification process and the techniques in approaching the solution for complexity. In the present scenario, efficient verification involving less time consumption and accuracy in working is required and essential. Therefore, UVM, a standardized verification methodology, was employed to verify the functionality of the test bench. The verification process faces several challenges, including complex processor architectures, the need for efficient verification techniques, and ensuring thorough coverage of all functional aspects. To address these challenges, recent techniques in constrained random verification and the utilization of UVM’s object-oriented programming (OOP) features are employed. This study aims to develop an efficient and comprehensive verification of the driver module for the Five-Stage Pipelined MIPS Processor using UVM. The driver module in the MIPS Processor facilitates the handling and coordination of input signals, ensuring proper communication and synchronization between various components. It plays a crucial role in driving the execution of instructions and managing the flow of data within the processor.