Memristor based Bit Multipliers

These days in the electronic industry research and work are at its boom for area scaling, interconnection delay, and less power consumption. On CMOS devices work has been already done as they were scaled down to a very small size, but for many applications CMOS alone is insufficient. Here, memristors can be put in use, as they show a wide range of capabilities to overcome problems regarding less interconnection delay, and lesser power consumption. In this paper, memristor based 2×2 and 3×3 multiplier is simulated with different approaches using MRL universal gates and it is compared with CMOS based multiplier and conventional memristor based multiplier. All the simulations for proposed memristor based multipliers are implemented at 45nm channel length of CMOS using the HSPICE-EDA tool.