A Systolic Array with Activation Stationary Dataflow for Deep Fully-Connected Networks

This paper presents an activation stationary (AS) dataflow suitable for networks with pure fully-connected (FC) layers. It is shown that the proposed AS dataflow can help to reduce the required memory size in hardware design and optimize energy efficiency by reducing data movement. Based on the AS dataflow, an output stationary (OS) systolic array is proposed to compute FC networks. To evaluate the proposed design, we further implement an accelerator for the FC-based implicit representation for MRI (IREM) algorithm. A proofof-concept demonstration system is developed based on field programmable gate array (FPGA). To evaluate the proposed design, We also map the IREM accelerator to 40nm CMOS technology and compare it with CPU, GPU-based and ASIC implementations.