RRAM-Based Precision-Scaleable Computing-In-Memory Scheme and Its Error Correction Approach

Resistive random access memories (RRAM) based Computing-in-memory (CIM) architecture has attracted enormous attention due to its high energy efficiency. However, the conductance states of RRAM devices are usually limited to 1-4bit which is much lower than the desired 8/16-bit precision, and the additional cost (such as the differential circuit) to map a negative parameter into positive conductance is large, leading to either large accuracy loss or low hardware efficiency. In this work, we propose an efficient precision-scaleable CIM scheme for high-performance computation, by which high-bit (INT8/16) signed multiplication-accumulation (MAC) operation can be constructed using the practical 3-bit RRAM devices with the unbalanced bit-slice method. Next, we analyze both the systemic error caused by the non-zero conductance of devices (when representing the bit of 0) and random errors caused by the conductance variation issue in the device. A linear regression correction approach is proposed to reduce the computation error. Finally, the proposed method is verified in terms of both software accuracy and hardware efficiency, the simulated result shows it is a promising method to be used in practical applications.