Effect of Silicon Substrate Roughness on Silver-Based Backside Metallization for Power Electronics Packaging

In this paper, a challenge of silver-based backside metallization (BSM) is addressed by investigating the effect of silicon (Si) substrate rear surface modification through chemical etching (roughness modification) on a sputtered Titanium/Nickel Vanadium/Silver (TiNiVAg) BSM stack in terms of structural (layers conformability, uniformity, morphology, etc.) properties. Ultra-flat (non-structured) and structured Si wafers using isotropic chemical etching with an average roughness (Ra) of 0nm and 200nm respectively, were used for this investigation. Cross-section access to the substrate-BSM stack was prepared by Focused on Beam (FIB) technique. Transmission electron microscopy (TEM) with field emission TEM (FE-TEM) and scanning TEM (STEM) modes, alongside energy dispersive X-ray (EDX) mapping and line scanning were used for this investigation. The TiNiVAg BSM deposited on the non-structured Si sample (Ra=0nm) showed a well-defined and defects-free conformably deposited metal layer stack structure with a preserved NiV columnar growth. On the other hand, the TiNiVAg BSM stack deposited on the structured Si wafer (Ra=200nm) showed significant morphological changes with nodular and needle-like defects in the Ag layer and at the Ag/NiV interface, which are thought to be caused by a disturbed NiV growth mechanism generating microcracks and seed defects at the Ag/NiV interface. The porous nature of these defects is most likely responsible for the Ag layer’s atmospheric corrosion with sulfur.