Analog NVM Synapse for Hardware-Aware Neural Network Training Optimization on 65nm CMOS TaOₓ ReRAM Devices

Deep Learning (DL) applications using Analog Neuromorphic Network (ANN) applications require linear, symmetric, and multilevel conductance modulation for high accuracy results. These requirements have led to the heavy use of GPUs for ANN applications. However, due to large power requirements for ANN, Non-Volatile Memory (NVM) devices such as Resistive Random Access Memory (ReRAM) are being investigated due to their lower power and lower area usage compared to conventional CMOS. In this work, using our 65nm CMOS integrated TaO
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ReRAM devices, we explore the effects of parameter adjustment for voltage and current controlled device operation in constant pulse programming cases and operational differences with incremental pulse programming. We present a simple statistical model for symmetry and linearity and explore the effect of linearity mismatch on cycle-to-cycle variability, switching pulse variation, and finally the effect on Neural Network (NN) learning using a “Cross-Sim” simulator trained on the MNIST dataset for handwritten digit recognition.