A Power-Efficient Successive Approximation Algorithm for Low-Activity Signals

This paper presents a new successive approximation algorithm that can digitize the second-order difference of signal samples rather than each sample point individually or plain difference of sample points. This method is able to drastically reduce the number of comparisons required to convert a new signal sample to digital numbers, from a fixed N comparisons commonly used in a conventional successive-approximation-register (SAR) analog-to-digital converter (ADC), to a number in between 2 and N for almost all the signal samples in an N-bit ADC. This proposed algorithm is implemented in MATLAB and tested on electrocardiogram (ECG) signals in this work. The experimental results show that our algorithm can reduce the number of comparisons by 58.75% compared to the conventional SAR ADC, and by 17.78% or more compared to several other state-of-the-art methods. In addition, it is able to reduce the DAC updating time by the same percentages, leading to lower power consumption in both DAC and digital parts of SAR ADC.